The present invention relates to an operating method of a memory device and, more particularly, to a memory device and a program verify method, in which the number of program verifications for a Multi-Level Cell (hereinafter, referred to as “MLC”) can be reduced.
A well-known NAND flash memory device includes a memory cell array, a row decoder and a page buffer. The memory cell array includes a plurality of cell strings intersected by a plurality of word lines, extending along the rows, and a plurality of bit lines and the bit lines, extending along the columns.
The row decoder connected to a string select line, word lines and a common source line is disposed on one side of the memory cell array, and the page buffer connected to a plurality of bit lines is disposed on the other side of the memory cell array.
In recent years, in order to further improve the level of integration of flash memory, active research has been done on a MLC capable of storing a plurality of data bits in one memory cell. This type of a memory cell is referred to as a MLC. A memory cell configured to store a single bit is referred to as a Single Level Cell (hereinafter, referred to as “SLC”).
FIG. 1a shows cell distributions of a SLC memory device.
Referring to FIG. 1a, the SLC has distributions of two cell states 101 and 102. In the SLC, the erase cell state 101 basically moves to the program cell state 102 according to the program operation (S110). The SLC requires one program operation as illustrated in FIG. 1a, and can complete the verify operation by performing one verification using verify voltage PV.
FIG. 1b shows cell distributions of a MLC memory device.
FIG. 1b also illustrates cell distributions of a MLC capable of storing 2-bit data. The MLC memory device has cell states 111 to 114 respectively representing data storage states [11], [10], [00] and [01]. The cell distributions correspond to threshold voltage distributions of the MLC.
Further, programming each cell includes performing a Least Significant Bit (LSB) program (S121) to program the cell into the state [10], and a Most Significant Bit (MSB) program includes programming the state [10] into the state [00] (S131) or the state [11] into the state [01] (S132).
After programming, verification is performed. In general, as the number of data bits that can be stored increases, cell distributions are increased. Thus, the number of verifications is also increased.
As mentioned above, in the case of the SLC, once verification is performed on a program 1 pulse. However, in the case of the MLC capable of storing 2-bit data as illustrated in FIG. 1b, two verifications are required on a program 1 pulse in the MSB program. In this manner, a 3-bit MLC requires three verifications on the program pulse, and a 4-bit MLC requires four verifications.
From the following Equation 1, it can be seen that as the number of verifications increases, the program time increases.Tpgm=(tPGM+tVfy×NVfy)×Npgm  (1)
where Tpgm is the total program time, tPGM is the program pulse time, tVfy is the verification time, NVfy is the number of verifications per program pulse, and Npgm is the number of applied program pulses.
As illustrated in Equation 1, as the number of verifications increases, the program time is lengthened, affecting the efficiency of a memory device.